1. Field of the Invention
The present invention relates to a semiconductor integrated circuit for driving a liquid crystal display panel, and more specifically to a method for driving an active matrix liquid crystal display panel having a TFT (thin film transistor) associated to each display element.
Description of Related Art
Liquid crystal display devices have various excellent features in comparison with other display devices such as a plasma display panel (PDP) and electrochemical display (ECD). For example, the liquid crystal display devices is suitable to be driven with a battery cell, since it needs only as small consumed power as a few microwatts per square centimeter. In addition, the liquid crystal display devices can be driven with a semiconductor circuit since it has only an operating voltage on the order of a few volts. Therefore, these features enable a flat screen display in combination with a semiconductor integrated circuit. Furthermore, as a matter of course in the display, a scale-up of the display size, a high definition and a multi-coloring have been demanded. To improve a contrast for satisfying these demands, there was proposed an active matrix display panel using a TFT associated with each of pixels.
For example, Japanese Patent Application Laid-open Publication 3P-A-03-035218 proposes one typical conventional method for driving a liquid crystal display panel. In this proposed method, for an AC driving of the liquid crystal display, a DC voltage to be applied is inverted from one field to another. In addition, each liquid crystal pixel or cell inevitably has a parasitic capacitance between a pixel electrode and a scan signal line and a video signal line.
Referring to FIG. 1, there is shown an equivalent circuit of one pixel of an active matrix liquid crystal display panel. In the drawing, Reference Signs Yn-1 and Yn designate a video signal line, and Reference Signs Xn-1 and Xn designate a scan signal line. These video signal lines and scan signal lines are arranged to form a matrix plane. At each of intersections between the video signal lines and the scan signal lines, one thin film transistor TFT is located. The shown thin film transistor TFT has a source (or drain) electrode connected to a corresponding video signal line Yn and a gate electrode connected to a corresponding scan signal line Xn. A drain (or source) electrode of the shown thin film transistor TFF is connected to a pixel electrode symbolically with a dot 10. A liquid crystal is sandwiched between this pixel electrode 10 and a not-shown opposing electrode which is in common to all pixels. Therefore, the liquid crystal itself has a capacitance CLC. In addition, a not-shown storage capacitor is connected between the drain (or source) electrode of the shown thin film transistor TFT and a just preceding or succeeding scan signal line. Furthermore, each pixel involves a parasitic capacitance including capacitances CX1, CX2, CY1 and CY2 which are formed between the pixel electrode 10 and the scan signal lines Xn and Xn-1 and the video signal lines Yn and Yn-1, respectively, and an overlap capacitance CGS between the gate electrode and a source region in the thin film transistor TFT. In addition, because of this capacitance CGS, when a gate voltage changes from an ON voltage to an OFF voltage, a drain voltage drops, and correspondingly, a voltage applied to the pixel electrode drops.
Now, operation will be described with reference to a waveform diagram of FIG. 2 illustrating a change in voltage in various electrodes when the active matrix liquid crystal display panel is driven. In FIG. 2, Vd, Vsc, Vs and Vg indicate a potential of the pixel electrode 10, a voltage of the opposing electrode, and a source voltage and a gate voltage of the thin film transistor TFT, respectively.
When the gate voltage Vg is at a high level, the pixel electrode 10 is charged to the source voltage Vs. Namely, the potential Vd of the pixel electrode 10 becomes as shown by a dot "A" on the voltage curve Vd. Then, when the gate voltage Vg drops to a low level or OFF voltage, the pixel electrode voltage Vd immediately drops by .DELTA.V, as shown a dot "B" on the voltage curve Vd. This drop voltage .DELTA.V is called a "feed-through" voltage, and can be expressed as follows, by assuming that the amount of voltage change in the scan signal (namely, the amplitude of the gate voltage) is .DELTA.Vg: EQU .DELTA.V=.DELTA.Vg.multidot.{CGS/(GLC+CGS)}
In the above mentioned conventional technique, the change storage electrode (storage capacitor) is formed by utilizing a portion of the thin film transistor connected to the just preceding scan signal line. The above referred Japanese patent publication adopts a feed-through compensating method by supplying another modulation signal to a scan signal applied to the gate electrode of the thin film transistor for turning on the thin film transistor, and by changing the polarity of the modulation signal from an even-numbered thin film transistor gate electrode to an odd-numbered thin film transistor gate electrode and vice versa, and further, by inverting this relation of the modulation signal from an odd-numbered field to an even-numbered field and vice versa.
Referring to FIGS. 3A to 3E, there are shown waveform diagrams illustrating a change in voltage in various electrodes in the conventional feed-through compensating method. FIG. 3A shows the waveform of a signal applied to the gate electrode of the thin film transistor connected to an (n-1)th scan signal line Xn-1, and FIG. 3B shows the waveform of a signal applied to the gate electrode of the thin film transistor connected to an (n)th scan signal line Xn. FIG. 3C illustrates a constant voltage which is applied to the opposing electrode, and which is equal to an averaged value of a video signal voltage. FIG. 3D indicates the waveform of the video signal applied to the source electrode of the thin film transistor. FIG. 3E represents the change in voltage on the pixel electrode. As will be apparent, modulation signal voltage Vge is supplied to the gate electrode, in addition to the scan signal voltage Vg.
In accordance with the conventional feed-through compensating method shown in FIGS. 3A to 3E, now consider to make zero (0) the potential change on the pixel electrode caused by the capacitance coupling in a thin film transistor connected to an (n)th scan signal line in a given field. Assuming that a positive modulating signal and a negatived modulation signal in comparison to Vge=0 are Vge(+) and Vge(-), respectively, the gate-source capacitance of the thin film transistor is CGS and the capacitance of the storage capacitor is Cs, the voltage change .DELTA.V on the pixel electrode can be expressed as follows: EQU .DELTA.V=-Vg.multidot.CGS/Ct+Vge.multidot.Cs/Ct
where Ct=Cs+Ct+CLC
The potential change caused by the capacitance coupling in a thin film transistor connected to the (n)th scan signal line in a field next to the given field, can be expressed as follows: EQU .DELTA.V=-Vg.multidot.CGS/Ct-Vge.multidot.Cs/Ct
Accordingly, since it is sufficient if both of the above equations are zero (0) in order to make zero the potential change in the odd-numbered fields and the even-numbered fields, Vge(-) and Vge(+) are determined to fulfill Vge(+)=-Vg(CGS/Cs) and Vge(-)=Vg(CGS/Cs).
FIG. 3E shows that the pixel electrode voltage does not change (at "A" and "B") during a period other than a transition period in which the scan signal voltage Vg and the modulation signal Vge are applied.
In the above mentioned conventional feed-through compensating method, however, the modulation signal has to be greatly changed not only from the even-numbered scan signal line to the odd-numbered scan signal line and vice versa, but also from the odd-numbered field to the even-numbered field and vice versa. Therefore, a driving circuit inevitably becomes complicated.